The IBM ASIC/SoC

This paper describes the methodology employed by the IBM Microelectronics Division for the design of its Blue Logic applicationspecific integrated circuits (ASICs) and system-on-a-chip (SoC) designs. This methodology is used by both IBM ASIC and SoC designers, as well as OEM customers. A key focus of the IBM ASIC/SoC methodology, outlined in the first section of this paper, is the first-time-right methods of design and verification that maximize correct operation of the chip upon product integration. The second section of this paper describes advances in methodology that deal with the physical effects of shrinking device geometries and enable design using the performance and density capabilities available in the new technologies, and methodology advances that have improved design turnaround time (TAT) for large, complex designs. Upcoming nanometerlevel technologies present new opportunities to integrate systems on a single chip, including functional components of mixed libraries and mixed analog and digital design. The final section of this paper outlines strategies that are enabling SoC design at these levels. Introduction While the device dimensions and structures, chip capacities, performance levels, and diversity and range of intellectual property (IP) in the VLSI and ASIC/SoC industries are most frequently described by silicon product vendors, the methods and execution time of the underlying design and integration processes are also critical factors in the success of product designers. Starting more than thirty years ago, based on the need to integrate multi-million-gate computer systems from thousands of hundred-gate chip designs, the modern ASIC industry is on the threshold of 100-million-gate chip design capability. Now many processors can be integrated onto a single system-on-a-chip (SoC). Although multimillion-gate ASIC and SoC designs are now routinely manufactured, designing them correctly and producing them on time, and in volume, with adequate quality/reliability levels, all involve the methodology of design. ASIC/SoC methodologies are needed that offer designers the integration of systems with a complete range of reusable digital and analog functions, and ways to integrate them onto a single chip [1]. Electronic design automation (EDA) companies are focusing as much on tool flow and integration as on the development of traditional standalone tools in order to relieve the complexity burden of ASIC/SoC design [2]. Finally, a